functional block diagrams in1 in2 in3 in4 s1 d1 s2 d2 s3 d3 s4 d4 adg431 in1 in2 in3 in4 s1 d1 s2 d2 s3 d3 s4 d4 adg432 in1 in2 in3 in4 s1 d1 s2 d2 s3 d3 s4 d4 adg433 switches shown for a logic "1" input rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a lc 2 mos precision quad spst switches adg431/adg432/adg433 features 44 v supply maximum ratings 15 v analog signal range low on resistance (<24 ) ultralow power dissipation (3.9 w) low leakage (<0.25 na) fast switching times t on <165 ns t off <130 ns break-before-make switching action ttl/cmos compatible plug-in replacement for dg411/dg412/dg413 applications audio and video switching automatic test equipment precision data acquisition battery powered systems sample hold systems communication systems general description the adg431, adg432 and adg433 are monolithic cmos devices comprising four independently selectable switches. they are designed on an enhanced lc 2 mos process which provides low power dissipation yet gives high switching speed and low on resistance. the on resistance profile is very flat over the full analog input range ensuring excellent linearity and low distortion when switching audio signals. fast switching speed coupled with high signal bandwidth also make the parts suitable for video signal switching. cmos construction ensures ultralow power dissipa- tion making the parts ideally suited for portable and battery powered instruments. the adg431, adg432 and adg433 contain four indepen- dent spst switches. the adg431 and adg432 differ only in that the digital control logic is inverted. the adg431 switches are turned on with a logic low on the appropriate control input, while a logic high is required for the adg432. the adg433 has two switches with digital control logic similar to that of the adg431 while the logic is inverted on the other two switches. each switch conducts equally well in both directions when on and has an input signal range which extends to the supplies. in the off condition, signal levels up to the supplies are blocked. all switches exhibit break before make switching action for use in multiplexer applications. i nherent in the design is low charge injection for minimum transients when switching the digital inputs. product highlights 1. extended signal range the adg431, adg432 and adg433 are fabricated on an enhanced lc 2 mos process giving an increased signal range which extends fully to the supply rails. 2. ultralow power dissipation 3. low r on 4. break-before-make switching this prevents channel shorting when the switches are config- ured as a multiplexer. 5. single supply operation for applications where the analog signal is unipolar, the adg431, adg432, and adg433 can be operated from a single rail power supply. the parts are fully specified with a single 12 v power supply and will remain functional with single supplies as low as 5 v. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001
adg431/adg432/adg433?pecifications 1 dual supply b version ?0 c to parameter +25 c +85 c unit test conditions/comments analog switch analog signal range v dd to v ss v r on 17 ? typ v d = 8.5 v, i s = ?0 ma; 24 26 ? max v dd = +13.5 v, v ss = ?3.5 v r on vs. v d (v s ) 15 % typ r on drift 0.5 %/ c typ r on match 5 % typ v d = 0 v, i s = ?0 ma leakage currents v dd = +16.5 v, v ss = 16.5 v source off leakage i s (off) 0.05 na typ v d = 15.5 v, v s = 15.5 v; 0.25 2 na max test circuit 2 drain off leakage i d (off) 0.05 na typ v d = 15.5 v, v s = 15.5 v; 0.25 2 na max test circuit 2 channel on leakage i d , i s (on) 0.1 na typ v d = v s = 15.5 v; 0.35 3 na max test circuit 3 digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.02 a max c in digital input capacitance 9 pf typ dynamic characteristics 1 v dd = +15 v, v ss = ?5 v t on 90 ns typ r l = 300 ? , c l = 35 pf; 165 ns max v s = 10 v; test circuit 4 t off 60 ns typ r l = 300 ? , c l = 35 pf; 130 ns max v s = 10 v; test circuit 4 break-before-make time delay, t d 25 ns typ r l = 300 ? , c l = 35 pf; (adg433 only) v s1 = v s2 = +10 v; test circuit 5 charge injection 5 pc typ v s = 0 v, r s = 0 ? , c l = 10 nf; test circuit 6 off isolation 68 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 7 channel-to-channel crosstalk 85 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 8 c s (off) 9 pf typ f = 1 mhz c d (off) 9 pf typ f = 1 mhz c d , c s (on) 35 pf typ f = 1 mhz power requirements v dd = +16.5 v, v ss = ?6.5 v digital inputs = 0 v or 5 v i dd 0.0001 a typ 0.1 0.2 a max i ss 0.0001 a typ 0.1 0.2 a max i l 0.0001 a typ 0.1 0.2 a max power dissipation 7.7 w max notes 1 guaranteed by design, not subject to production test. specifications subject to change without notice. rev. c C2C (v dd = +15 v 10%, v ss = ?5 v 10%, v l = +5 v 10%, gnd = o v, unless otherwise noted.)
truth table (adg431/adg432) adg431 in adg432 in switch condition 01on 1 0 off truth table (adg433) logic switch 1, 4 switch 2, 3 0 off on 1 on off single supply b version ?0 c to parameter +25 c +85 c unit test conditions/comments analog switch analog signal range 0 v to v dd v r on 28 ? typ 0 < v d < 8.5 v, i s = ?0 ma; 42 45 ? max v dd = 10.8 v r on vs. v d (v s ) 20 % typ r on drift 0.5 %/ c typ r on match 5 % typ v d = 0 v, i s = ?0 ma leakage currents v dd = 13.2 v source off leakage i s (off) 0.04 na typ v d = 12.2/1 v, v s = 1/12.2 v; 0.25 2 na max test circuit 2 drain off leakage i d (off) 0.04 na typ v d = 12.2/1 v, v s = 1/12.2 v; 0.25 2 na max test circuit 2 channel on leakage i d , is (on) 0.01 na typ v d = v s = 12.2 v/1 v; 0.3 3 na max test circuit 3 digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.01 a max c in digital input capacitance 9 pf typ dynamic characteristics 1 v dd = 12 v, v ss = 0 v t on 165 ns typ r l = 300 ? , c l = 35 pf; 240 ns max v s = 8 v; test circuit 4 t off 60 ns typ r l = 300 ? , c l = 35 pf; 115 ns max v s = 8 v; test circuit 4 break-before-make time delay, t d 25 ns typ r l = 300 ? , c l = 35 pf; (adg433 only) v s1 = v s2 = 10 v; test circuit 5 charge injection 25 pc typ v s = 0 v, r s = 0 ? , c l = 10 nf; test circuit 6 off isolation 68 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 7 channel-to-channel crosstalk 85 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 8 c s (off) 9 pf typ f = 1 mhz c d (off) 9 pf typ f = 1 mhz c d , c s (on) 35 pf typ f = 1 mhz power requirements v dd = 13.2 v digital inputs = 0 v or 5 v i dd 0.0001 a typ 0.03 0.1 a max i l 0.0001 a typ 0.03 0.1 a max v l = 5.25 v power dissipation 1.9 w max notes 1 guaranteed by design, not subject to production test. specifications subject to change without notice. (v dd = 12 v 10%, v ss = o v, v l = 5 v 10%, gnd = o v, unless otherwise noted) adg431/adg432/adg433 rev. c C3C
adg431/adg432/adg433 rev. c C4C absolute maximum ratings (t a = 25 c unless otherwise noted.) v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +25 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to ?5 v v l to gnd . . . . . . . . . . . . . . . . . . . . . . ?.3 v to v dd + 0.3 v analog, digital inputs 2 . . . . . . . . . . v ss ?2 v to v dd + 2 v or 30 ma, whichever occurs first continuous current, s or d . . . . . . . . . . . . . . . . . . . . . 30 ma peak current, s or d . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ma (pulsed at 1 ms, 10% duty cycle max) operating temperature range industrial (b version) . . . . . . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c plastic package, power dissipation . . . . . . . . . . . . . . 470 mw ja , thermal impedance . . . . . . . . . . . . . . . . . . . . 117 c/w lead temperature, soldering (10 sec) . . . . . . . . . . . . 260 c soic package, power dissipation . . . . . . . . . . . . . . . 600 mw ja , thermal impedance . . . . . . . . . . . . . . . . . . . . . 77 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. 2 overvoltages at in, s or d will be clamped by internal diodes. current should be limited to the maximum ratings given. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adg431/adg432/adg433 features proprietary esd protection circuitry, perma- nent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of f unctionality. pin configuration (dip/soic) top view (not to scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 in1 d1 s1 v ss gnd s4 d4 in4 in2 d2 s2 v dd v l s3 d3 in3 adg431 adg432 adg433 ordering guide model temperature range package option 1 adg431bn ?0 c to +85 c n-16 adg431br ?0 c to +85 c r-16a adg431abr ?0 c to +85 c r-16a 2 adg432bn ?0 c to +85 c n-16 adg432br ?0 c to +85 c r-16a adg432abr ?0 c to +85 c r-16a 2 adg433bn ?0 c to +85 c n-16 adg433br ?0 c to +85 c r-16a adg433abr ?0 c to +85 c r-16a 2 notes 1 n = plastic dip; r = 0.15" small outline ic (soic). 2 trench isolated, latch-up proof parts. see trench isolation section. terminology v dd most positive power supply potential. v ss most negative power supply potential in dual supplies. in single supply applications, it may be connected to gnd. v l logic power supply (5 v). gnd ground (0 v) reference. s source terminal. may be an input or output. d drain terminal. may be an input or output. in logic control input. r on ohmic resistance between d and s. r on vs. v d (v s ) the variation in r on due to a change in the ana- log input voltage with a constant load cur rent. r on drift change in r on vs. temperature. r on match difference between the r on of any two switches. i s (off) source leakage current with the switch ?ff. i d (off) drain leakage current with the switch ?ff. i d , i s (on) channel leakage current with the switch ?n. v d (v s ) analog voltage on terminals d, s. c s (off) ?ff?switch source capacitance. c d (off) ?ff?switch drain capacitance. c d , c s (on) ?n?switch capacitance. c in input capacitance to ground of a digital input. t on delay between applying the digital control input and the output switching on. t off delay between applying the digital control input and the output switching off. t d ?ff?time or ?n?time measured between the 90% points of both switches, when switching from one address state to another. crosstalk a measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. off isolation a measure of unwanted signal coupling through an ?ff?switch. charge a measure of the glitch impulse transferred from the injection digital i nput to the analog output during switching. warning! esd sensitive device
v d or v s ?drain or source voltage ?v 50 40 10 ?0 ?0 r on ? 01020 30 20 t a = 25 c v l = 5v 0 v dd = +15v v ss = ?5v v dd = +10v v ss = ?0v v dd = +12v v ss = ?2v v dd = +5v v ss = ?v tpc 1. on resistance as a function of v d (v s ) dual supplies v d or v s drain or source voltage v 50 40 10 20 10 r on 01020 30 20 0 v dd = +15v v ss = 15v v l = +5v 125 c 85 c 25 c tpc 2. on resistance as a function of v d (v s ) for different temperatures temperature c 10 0.001 20 120 40 leakage current na 60 80 100 1 0.1 0.01 v dd = +15v v ss = 15v v l = +5v 140 v s = 15v v d = 15v i s (off) i d (off) i d (on) tpc 3. leakage currents as a function of temperature v d or v s drain or source voltage v 50 40 10 05 r on 10 15 20 30 20 t a = 25 c v l = 5v 0 v dd = 15v v ss = 0v v dd = 10v v ss = 0v v dd = 12v v ss = 0v v dd = 5v v ss = 0v tpc 4. on resistance as a function of v d (v s ) single supply frequency hz 100ma 100na 10 10m 100 i supply 1k 10k 100k 1m 10ma 1ma 100 a 10 a 1 a v dd = +15v 4 sw v ss = 15v v l = +5v 1 sw i+, i i l tpc 5. supply current vs. input switching frequency v d or v s drain or source voltage v 0.04 0.02 0.04 20 10 leakage current na 01020 0.00 0.02 v dd = +15v v ss = 15v t a = +25 c v l = +5v i d (on) i s (off) i d (off) tpc 6. leakage currents as a function of v d (v s ) typical performance characteristics adg431/adg432/adg433 rev. c C5C
adg431/adg432/adg433 rev. c C6C frequency hz 120 100 40 100 10m 1k off isolation db 10k 100k 1m 80 60 v dd = +15v v ss = 15v v l = +5v tpc 7. off isolation vs. frequency frequency hz 110 100 60 100 10m 1k crosstalk db 10k 100k 1m 90 80 70 v dd = +15v v ss = 15v v l = +5v tpc 8. crosstalk vs. frequency trench isolation in the adg431a, adg432a and adg433a, an insulating oxide layer (trench) is placed between the nmos and pmos transistors of each cmos switch. parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, the result being a completely latch-up proof switch. in junction isolation, the n and p wells of the pmos and nmos transistors from a diode that is reverse-biased under normal operation. however, during overvoltage conditions, this diode becomes forward biased. a silicon-controlled rectifier (scr) type circuit is formed by the two transistors causing a significant amplification of the current which, in turn, leads to latch up. with trench isolation, this diode is removed, the result being a latch-up proof switch. buried oxide layer substrate (backgate) t r e n c h t r e n c h t r e n c h p + p + p-channel n + n + n-channel p n v g v d v s v g v d v s figure 1. trench isolation application figure 2 illustrates a precise, fast sample-and-hold circuit. an ad845 is used as the input buffer while the output opera- tional amplifier is an ad711. during the track mode, sw1 is closed and the output v out follows the input signal v in . in the hold mode, sw1 is opened and the signal is held by the hold capaci tor c h . due to switch and capacitor leakage, the voltage on the hold capacitor will decrease with time. the adg431/adg432/ adg433 minimizes this droop due to its low leakage specifica- tions. the droop rate is further minimized by the use of a polystyrene hold capacitor. the droop rate for the circuit shown is typically 30 v/ s. a second switch sw2, which operates in parallel with sw1, is included in this circuit to reduce pedestal error. since both switches will be at the same potential, they will have a differen- tial e ffect on the op amp ad711 which will minimize charge injection effects. pedestal error is also reduced by the compensa- tion network r c and c c . this compensation network also reduces the hold time glitch while optimizing the acquisition time. using the illustrated op amps and component values, the pedestal error has a maximum value of 5 mv over the 10 v input range. both the acquisition and settling times are 850 ns. +15v 15v 2200pf r c 75 c c 1000pf c h 2200pf v out adg431 adg432 adg433 sw1 sw2 s s d d +15v +5v 15v ad845 +15v 15v v in ad711 figure 2. fast, accurate sample-and-hold
adg431/adg432/adg433 rev. c C7C test circuits i ds v1 sd v s r on = v1/i ds test circuit 1. on resistance sd +15v +5v 0.1 f 0.1 f v dd v l in v s gnd v ss r l 300 c l 35pf v out 0.1 f 15v t on t off 3v 50% 50% 50% 50% 3v 90% 90% v in v in v out adg431 adg432 test circuit 4. switching times s1 d1 +15v +5v 0.1 f 0.1 f v dd v l in1, in2 v s1 gnd v ss r l1 300 c l1 35pf v out1 0.1 f 15v v s2 v out2 r l2 300 c l2 35pf s2 v in d2 t d t d 3v 50% 50% 90% v in v out1 v out2 90% 90% 90% 0v 0v 0v test circuit 5. break-before-make time delay sd +15v +5v v dd v l in v s gnd v ss c l 10nf v out 15v r s 3v v in v out v out q inj = c l v out test circuit 6. charge injection sd v s a v d a i s (off) i d (off) test circuit 2. off leakage sd v s v d a i d (on) test circuit 3. on leakage
adg431/adg432/adg433 rev. c C8C c00050bC0C3/01(c) printed in u.s.a. 16-lead plastic dip (narrow) (n-16) 16 18 9 0.840 (21.34) 0.745 (18.92) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.26) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) sd +15v +5v 0.1 f 0.1 f v dd v l in v s gnd v ss r l 50 v out 0.1 f 15v v in test circuit 7. off isolation outline dimensions dimensions shown in inches and (mm). 16-lead soic (r-16a) 16 9 8 1 0.3937 (10.00) 0.3859 (9.80) 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) pin 1 seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) bsc 0.0099 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 sd +15v +5v 0.1 f 0.1 f v dd v l v s gnd v ss 50 nc 0.1 f 15v v in1 v in2 s d r l 50 v out channel-to-channel crosstalk = 20 log v s /v out test circuit 8. channel-to-channel crosstalk adg431/adg432/adg433 revision history location page data sheet changed from rev. b to rev. c. changes to specifications table (dual supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to specifications table (single supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 16-lead cerdip deleted from outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
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